1. Field of the Invention
The present invention relates to a thyristor and a method of manufacturing the same, and more particularly, it relates to an improvement in an MCT (MOS controlled thyristor).
2. Description of the Background Art
FIG. 11 is a sectional view showing a conventional MCT. Referring to FIG. 11, an n-type epitaxial layer 2a is formed on a p.sup.+ -type semiconductor substrate 1, and an n.sup.- -type epitaxial layer 2b is formed on the n-type epitaxial layer 2a. The n-type epitaxial layer 2a and the n.sup.- -type epitaxial layer 2b define an n-type base layer 2. A p-type well region 3 is formed on the surface of the n-type base layer 2, by selectively diffusing a p-type impurity. An n.sup.+ -type diffusion region 4 is formed on a central portion of the surface of the p-type well region 3 by selectively diffusing an n-type impurity of high concentration, while an n-type diffusion region 5 is formed adjacently to the n.sup.+ -type diffusion region 4 by selectively diffusing an n-type impurity into an outer peripheral portion of the n.sup.+ -type diffusion region 4. A p.sup.+ -type diffusion region 6 is formed over the n.sup.+ -type diffusion region 4 and the n-type diffusion region 5 by selectively diffusing a p-type impurity of high concentration into a region around the boundary between the surfaces of the regions 4 and 5. A gate insulating film 7 of an oxide is formed on the surfaces of the p-type well region 3 and the n-type diffusion region 5 which are held between the surfaces of the n-type base layer 2 and the p.sup.+ -type diffusion region 6, and a gate electrode 8 of polysilicon is formed on the gate insulating film 7. A cathode electrode 9 of a metal is provided in contact with the surfaces of the n.sup.+ -type diffusion region 4 and the p.sup.+ -type diffusion region 6. This cathode electrode 9 is isolated from the gate electrode 8 through an interlayer isolation film 10. On the other hand, an anode electrode 11 of a metal is formed on the back surface of the p.sup.+ -type semiconductor substrate 1.
FIG. 12 is a circuit diagram showing an equivalent circuit of the MCT shown in FIG. 11. The n-type base layer 2, the p-type well region 3 and the n.sup.+ -type diffusion region 4 serve as a collector, base and an emitter respectively to define an npn transistor Q1, while the p.sup.+ -type semiconductor substrate 1, the n-type base layer 2 and the p-type well region 3 serve as an emitter, base and a collector respectively to define a pnp transistor Q2. Further, the n-type diffusion region 5 and the n.sup.- -type epitaxial layer 2b serve as a source and a drain respectively and a surface part of the p-type well region 3 located just under the gate electrode 8 serves as a channel region to define an NMOS transistor Q3, while the p-type well region 3 and the p.sup.+ -type diffusion region 6 serve as a source and a drain respectively and a surface part of the n-type diffusion region 5 located just under the gate electrode 8 serves as a channel region to define a PMOS transistor Q4.
The operation is now described. In order to turn on the MCT shown in FIG. 11, the NMOS transistor Q3 is turned on for a prescribed time in such a state that the anode electrode 11 is at a higher potential than the cathode electrode 9. When a positive voltage is applied to the gate electrode 8, the NMOS transistor Q3 is turned on so that electrons are injected into the base of the pnp transistor Q2 through the channel formed in the vicinity of the surface part of the p-type well region 3 located just under the gate electrode 8. Then, the pnp transistor Q2 is turned on and a large quantity of holes flow toward its collector by the amplifying action of the transistor. These holes are supplied to the base of the npn transistor Q1, which is then turned on so that a large quantity of electrode flow toward its collector by the amplifying action of the transistor. These electrons are supplied to the base of the pnp transistor Q2, to further accordingly turn on the pnp transistor Q2. Thus, once the transistor Q2 is turned on, a positive feedback loop is defined between the transistors Q1 and Q2, whereby a thyristor formed by the transistors Q1 and Q2 is latched. Therefore, a current continuously flows between the anode electrode 11 and the cathode electrode 9 even if the NMOS transistor Q3 is turned off.
In order to turn off the MCT, on the other hand, the PMOS transistor Q4 is turned on for a prescribed time. When a negative voltage is applied to the gate electrode 8, the PMOS transistor Q4 is turned on so that holes to be injected into the base of the npn transistor Q1 are extracted by the cathode electrode 9 through the p.sup.+ -type diffusion region 6 through a channel formed in the vicinity of a surface part of the n-type diffusion region 5 located just under the gate electrode 8. Consequently, the npn transistor Q1 is turned off and hence the pnp transistor Q2 is also turned off, to release the thyristor from latching. Thus, the main current having flown between the anode electrode 11 and the cathode electrode 9 is cut off.
As hereinabove described, the MCT is turned on when a positive voltage is applied to the gate electrode 8, which is common to the MOS transistors Q3 and Q4, for a prescribed time, while the same is turned off when a negative voltage is applied to the gate electrode 8 for a prescribed time.
The aforementioned operation is enciphered as follows: Assuming the .alpha..sub.1 and .alpha..sub.2 represent current amplification factors of the bipolar transistors Q1 and Q2, I.sub.CO1 and I.sub.CO2 represent collector saturation currents and I.sub.g1 and I.sub.g2 represent ON-state currents of the MOS transistors Q3 and Q4, an anode current I.sub.A is expressed as follows: ##EQU1##
In turn-on operation, the current I.sub.g1 flows in the state of the current I.sub.g2 =0 as hereinabove described, whereby a base current I.sub.B2 of the transistor Q2 starts to flow and the transistor Q2 starts its operation. A collector current caused by the operation of the transistor Q2 is supplied as a base current I.sub.B1 of the transistor Q1, and the current flowing in the transistors Q1 and Q2 is increased. In general, the current amplification factors .alpha..sub.1 and .alpha..sub.2 are increased with increase of the current, whereby the anode current I.sub.A is acceleratively increased. The MCT enters an ON state in the following state: EQU .alpha..sub.1 +.alpha..sub.2 =1 (2)
In turn-off operation, on the other hand, the curent I.sub.g2 flows in the state of the current I.sub.g1 =0, as hereinabove described. It is assumed here that R.sub.1 represents a resistance component at the channel of the p-type well region 3 or the PMOS transistor Q4 with respect to the current I.sub.g2. Due to the flow of the current I.sub.g2, the current having flown into the transistor Q1 is reduced by an amount corresponding to the current I.sub.g2, and the value .alpha..sub.1 +.alpha..sub.2 is also reduced. A voltage drop I.sub.g2 R.sub.1 at the resistance component R.sub.1 is supplied as a base-to-emitter forward bias voltage of the transistor Q1. However, the current amplification factor .alpha..sub.1 of the transistor Q1 is abruptly reduced because this voltage is generally smaller so that electrons can not be injected into the base from the emitter of the transistor Q1. Consequently, the value .alpha..sub.1 +.alpha..sub.2 is also acceleratively reduced, so that the MCT is turned off when .alpha..sub.1 +.alpha..sub.2 &gt;1.
In the conventional MCT having the aforementioned structure, triple diffusion is required in order to form the structure of the p-type well region 3, the n.sup.+ -type and n-type diffusion regions 4 and 5, and the p.sup.+ -type diffusion region 6. Thus, the manufacturing steps are complicated. Further, since the characteristics of the MOS transistors Q3 and Q4 depend on degrees of impurity concentration in respective diffusion steps in the triple diffusion, it is difficult to independently set ON-state resistances and threshold voltages (i.e., turn-on and turn-off conditions) of the MOS transistors Q3 and Q4. In addition, the cathode electrode 9 must be in contact with the n.sup.+ -type diffusion region 4 and the p.sup.+ -type diffusion region 6, and hence the p-type well region 3 enclosing the same is inevitably increased in width to increase the resistance component R.sub.1. Since the current I.sub.g2 is in positive correlation with a cathode current I.sub.k, the voltage drop I.sub.g2 R.sub.1 at the resistance component R.sub.1 unpreferably reaches the voltage sufficient to inject electrons from the emitter to the base of the transistor Q1 and thus .alpha..sub.1 +.alpha..sub.2 &gt;1 if the current I.sub.g2 is fed with conduction of the MOS transistor Q4 in order to turn off the MCT in a high state of the cathode current I.sub.k, and hence the MCT cannot be turned off even if the MOS transistor Q4 is turned on.